The present invention relates to direct digital frequency synthesizers and, in particular, to a circuit and method for reducing the spurious levels of such direct digital frequency synthesizers.
Frequency synthesizer sub-systems using direct digital frequency synthesizers are used in modern communication systems. Direct digital frequency synthesizers have fast switching speeds, excellent temperature and aging stability and allows for phase continuous switching of the carrier signal. These characteristics make direct digital frequency synthesizers desirable for use in modern communication systems.
Prior art direct digital frequency synthesizers typically use a sinewave look-up table method. This method synthesizes a sinewave by using a phase accumulator to address a sine function look-up table stored in a read-only memory (ROM) or in a programmable read-only memory (PROM). The table converts the phase information provided by the accumulator into digital samples of a sinusoidal wave. The digital samples are converted by a digital to analog converter (DAC), which produces a staircase approximation of a sinewave in analog form. Each recalled sample differs from the previous sample by a constant phase increment and, thus different frequencies may be synthesized by changing the phase difference between the recalled samples. This is accomplished by changing the frequency control word (K value) to the phase accumulator.
Both the frequency and phase resolution of the synthesizer are determined by the word length of the phase accumulator. Typically, the word length of the accumulator maybe from 20 to 32 bits, but the number of accumulator output bits addressing the look-up table PROM is usually limited to 12 bits to minimize memory size, power, and space. It has been determined that the direct digital synthesizer output spurious levels are dependent upon the initial phase value at which the accumulator starts if the K value selected does not cause the least significant bit addressing the PROM to change. It has been observed that for a given output frequency of the direct digital synthesizer, that is, for a given K value, the spurious level out of the direct digital synthesizer may differ in amplitude when remeasured after several frequency changes, that is, changes in the K value input to the accumulator or when power is removed and reapplied to the circuit. This is caused by a different initial state or phase at which the accumulator starts. This has been a drawback in prior art direct digital synthesizers which put out undesired spurious levels. The present invention overcomes these drawbacks of the prior art.